1. Field of the Invention
The present invention relates to the field of semiconductor processing and more particularly to a two step deposition process for forming gate structures in MOS integrated circuits for improved lithography control coupled with a low overhead local interconnect.
2. Description of the Relevant Art
Integrated circuits employing MOS transistors have been widely known and extensively used in the electronics industry for over 30 years. The basic structure and processing sequence for forming an MOS transistor and MOS integrated circuits has been extensively described in the literature. Typically, a thin oxide is grown on a lightly doped silicon substrate. Thereafter, a gate structure is formed over the thin oxide layer typically by depositing polysilicon and patterning the polysilicon with conventional photolithography masking and etch techniques. After the MOS transistor gate has been formed, it is used as a mask for a subsequent implant during which source/drain structures are formed within the silicon substrate. The source/drain structures are of opposite conductivity type than the silicon substrate. Current flow between the source and drain structures is negligible under equilibrium conditions because back to back pn junctions exist between the source and drain structures. Upon application of an appropriate bias to the MOS transistor gate, however, a conductive channel is induced at the silicon-oxide interface providing a path between the source and drain structure through which current may flow upon appropriate biasing of the source and drain terminals. In this manner, the MOS transistor functions as a switch controlled by the transistor gate.
Present day semiconductor integrated circuits include a large number (i.e., greater than 10.sup.6) of MOS transistors fabricated within a single silicon substrate. The operating characteristics of each of these transistors are dictated, to a large extent, by the physical geometries of the transistors. It will be appreciated by those skilled in the art that small variations in operating characteristics of the individual transistors fabricated with a given semiconductor process may result in large an often unacceptable variations in the operating characteristics of the semiconductor device as a whole. For example, the speed of an integrated circuit, measured by the time required to complete a function, is related to the operating characteristics of the integrated circuits transistors. The saturated drain current I.sub.dsat represents the current flowing from the drain terminal to the source terminal when the gate is biased to induce a strong channel in the silicon substrate (i.e., V.sub.G &gt;V.sub.T where V.sub.T represents the transistor threshold voltage) and the drain terminal is strongly biased with respect to the source terminal (i.e., V.sub.DS &gt;=V.sub.G). The I.sub.dsat characteristic of a particular semiconductor process is a speed indicator because higher drain currents result in faster transistor switching times. The integrated circuit transistor gate, which functions as an input of the transistor in a typical configuration, has a small but finite capacitance associated with it. Because of the gate capacitance, the gate voltage cannot change instantaneously from an "on" value (i.e., .vertline.V.sub.G .vertline.&gt;=.vertline.V.sub.T .vertline.) to an "off" value. Instead, the output current from the preceding transistor stage, typically the drain current of the preceding stage, charges the gate capacitance such that the gate voltage transitions to a new value. It will be appreciated, therefore, that higher saturated drain current results in faster switching times for a typical integrated circuit.
It is well known in the field of semiconductor processing that the saturated drain current I.sub.dsat, to a first order approximation, varies directly with the width of the transistor and varies inversely with the length of the transistor. The desire to maximize I.sub.dsat has resulted in a steady trend within the semiconductor processing industry towards shorter and shorter channel lengths for integrated circuit transistors. With present day integrated circuit transistors, the channel length is not uncommonly less than one micron. In this submicron region, control of the integrated circuit transistor dimensions becomes increasingly important. Not only is it more important to fabricate smaller and smaller devices, it is equally important to minimize variations among the individual transistors comprising the integrated circuit. Minimizing transistor variability requires improved control over each aspect of the semiconductor process. Typical semiconductor processes include a transistor gate formation sequence in which polysilicon or other suitable material is deposited typically to a thickness in the range of approximately 1000 to 3000 angstroms and thereafter patterned with a photolithography/etch sequence. To minimize variability of the integrated circuit, it is desirable if the etch process used to form the transistor gate produces sidewalls that are substantially perpendicular to the upper surface of the semiconductor substrate. Typically, however, semiconductor processes including polysilicon etch processes result in sloped sidewall profiles. Sloped sidewalls in transistor gates are typically undesirable because the final dimension of the transistor gate varies with the vertical displacement above the oxide-gate interface. Referring to FIG. 1, a gate structure 10 is shown fabricated on a silicon dioxide layer 14 over a silicon substrate 20. Gate structure 10 includes a pair of sidewalls 12a and 12b. Sidewalls 12a and 12b extend between a gate upper surface 13 and a gate-oxide interface at an angle .alpha.. The slope of sidewalls 12a and 12b represented by the angle .alpha. produce a transistor gate 10 in which a lateral dimension d.sub.1 of transistor gate 10 near the gate-oxide interface is greater than a lateral dimension d.sub.2 describing the lateral dimension of gate 10 proximal to upper surface 13. It will be further appreciated that the discrepancy between the first lateral displacement d.sub.1 and the second lateral displacement d.sub.2 increases with increasing gate thickness t.sub.g. The sloped sidewalls 12a and 12b are undesirable because the lateral dimension of gate 10 as patterned with the photolithography/etch sequence varies from the as drawn dimension. It will be appreciated to those skilled in the art of semiconductor processing that the critical dimension or channel length of the transistor fabricated in FIG. 1 will be defined by the first displacement d.sub.1 typically resulting in transistor channel lengths that are greater than desirable. Furthermore, variability in the angle .alpha. results in further unwanted variations in the transistor channel length.
In addition to the variability control problems identified with respect to FIG. 1, typical semiconductor processes include a sequence for forming a so called local interconnect layer in addition to the process sequence used to fabricate transistor gate 10. In the typical semiconductor process, the transistor gate is fabricated with a single polysilicon deposition process. If a local interconnect is desired, it must be fabricated with a subsequent deposition of a conductive material. Dedicated processing steps such as a process step dedicated solely to the formation of semiconductor interconnects are typically undesirable because of the increased complexity and cost associated with additional processing.